1. Technical Field
The present invention relates to a frequency synthesizer device and a modulation frequency displacement adjustment method.
2. Related Art
Heretofore, a frequency synthesizer that uses a phase lock loop (PLL) circuit has been known. For example, in FIG. 9 of Japanese Patent Application Laid-Open (JP-A) No. 2-100519, a two-level frequency modulator is disclosed in which a frequency synthesizer and a digital-to-analog converter (DAC) are combined. The frequency synthesizer utilizes a PLL circuit, and, at times of frequency switching, the DAC applies a control voltage from outside the PLL circuit to a voltage-controlled oscillator.
A fractional-N frequency synthesizer is known as a frequency synthesizer that may control frequency with high precision. This synthesizer equivalently sets frequency division ratios to non-integer values using delta-sigma modulation or the like, and may vary an oscillation frequency continuously. A frequency synthesizer device 100 as illustrated in FIG. 17 has been known heretofore. The frequency synthesizer device 100 uses a fractional-N frequency synthesizer for a two-level frequency modulator. With this frequency synthesizer device 100, transmission data may be modulated by frequency shift keying (FSK) and transmitted.
As illustrated in FIG. 17, the frequency synthesizer device 100 includes a fractional-N frequency synthesizer 11, a digital-to-analog converter (DAC) 12, a voltage-controlled oscillator 14 and an adder 16.
The fractional-N frequency synthesizer 11 includes a delta-sigma modulator 18, a programmable frequency divider 20, a frequency phase comparator 22 and a loop filter 24.
Transmission data is inputted to the adder 16 and the DAC 12. The adder 16 inputs the transmission data and channel frequency setting data, which is data that corresponds to an oscillation frequency at which the voltage-controlled oscillator 14 is to oscillate (a carrier frequency).
The adder 16 adds the inputted transmission data and frequency setting data and outputs added data to the delta-sigma modulator 18.
The delta-sigma modulator 18 applies delta-sigma modulation to the inputted added data, and outputs the result to the programmable frequency divider 20 to serve as a frequency division ratio setting signal.
At the programmable frequency divider 20, the signal outputted from the voltage-controlled oscillator 14 is frequency-divided by the frequency division ratio specified by the frequency division ratio setting signal outputted from the delta-sigma modulator 18, and the frequency-divided signal is outputted to the frequency phase comparator 22.
The frequency phase comparator 22 compares the phases of an inputted reference clock and the frequency-divided signal outputted from the programmable frequency divider 20, and outputs a phase difference signal corresponding to the phase difference to the loop filter 24. The loop filter 24 applies smoothing processing to the inputted phase difference signal, and outputs the result to the voltage-controlled oscillator 14 to serve as a voltage control signal.
Meanwhile, the DAC 12 converts the inputted transmission data from digital to analog and outputs the analog signal to the voltage-controlled oscillator 14.
The voltage-controlled oscillator 14 oscillates at a frequency (a channel frequency) according to the voltage control signal inputted from the loop filter 24, and outputs a signal in which this frequency is FSK-modulated with the analog signal inputted from the DAC 12. For example, if a frequency displacement is ΔF, when the transmission data inputted to the DAC 12 is a one, an FSK-modulated signal that is shifted by +ΔF from the channel frequency is outputted from the voltage-controlled oscillator 14, and when the transmission data inputted to the DAC 12 is a zero, an FSK-modulated signal that is shifted by −ΔF from the channel frequency is outputted from the voltage-controlled oscillator 14.
Now, if the transmission data were a signal with a waveform as illustrated in FIG. 18 (1), and the voltage-controlled oscillator 14 were controlled only by the DAC 12, the FSK-modulated signal outputted from the voltage-controlled oscillator 14 would have a waveform as illustrated in FIG. 18 (3). If the signal outputted from the voltage-controlled oscillator 14 were modulated by control of the DAC 12 alone, as illustrated in FIG. 18 (3), the transmission data would not be inputted to the fractional-N frequency synthesizer 11 and the oscillator frequency would go into a locked state. As a result, the FSK-modulated signal would have characteristics of a high-pass filter. On the other hand, if the signal outputted from the voltage-controlled oscillator 14 were modulated by control of the fractional-N frequency synthesizer 11 alone, the FSK-modulated signal outputted from the voltage-controlled oscillator 14 would have a waveform as illustrated in FIG. 18 (4). As illustrated in FIG. 18 (4), a signal that was FSK-modulated by control of the fractional-N frequency synthesizer 11 alone would have characteristics of a low-pass filter.
That is, with the fractional-N frequency synthesizer 11 alone, if the bit rate of the transmission data increased, tracking in the PLL might be lost. Accordingly, the DAC 12 is combined into a two-level frequency modulator as in the frequency synthesizer device 100 illustrated in FIG. 17, and hence a properly FSK-modulated signal as illustrated in FIG. 18 (2) is outputted from the voltage-controlled oscillator 14 even when the transmission data is at a high bit rate.
However, because the frequency synthesizer device 100 features two modulation paths, it is difficult to match up frequency displacements of the two modulation paths when adjusting the frequency. In a fractional-N frequency synthesizer, the frequency displacement is controlled with high precision. Therefore, there is a need to suitably adjust the amplitude of the control voltage that is inputted from the DAC 12 to the voltage-controlled oscillator 14, which is a direct modulation path.